[mult.v]
//-----------------------------------------------------
// This is my sixth Verilog Design
// Design Name : mult
// File Name : mult.v
// Function : This is a 7 bit multiplier with
// Synchronous active high reset and
// with active high enable signal
//-----------------------------------------------------
module mult (
clock , // Clock input of the design
reset , // active high, synchronous Reset input
enable , // Active high enable signal for counter
a,b, // 4 bit vector output of the counter
y // 7bit result
); // End of port list
//-------------Input Ports-----------------------------
input clock ;
input reset ;
input enable ;
//-------------Output Ports----------------------------
output [3:0] a ;
output [3:0] b ;
output [6:0] y ;
//-------------Input ports Data Type-------------------
// By rule all the input ports should be wires
wire clock ;
wire reset ;
wire enable ;
//-------------Output Ports Data Type------------------
// Output port can be a storage element (reg) or a wire
reg [3:0] a ;
reg [3:0] b ;
reg [6:0] y ;

//------------Code Starts Here-------------------------
// Since this counter is a positive edge trigged one,
// We trigger the below block with respect to positive
// edge of the clock.
always @ (posedge clock)
begin : MULT // Block Name
  // At every rising edge of clock we check if reset is active
  // If active, we load the counter output with 8'b0000_0001
  if (reset == 1'b0) begin
    a <= #1 4'b0010;
    b <= #1 4'b0010;
  end
  // If enable is active, then we increment the counter
  else if (enable == 1'b1) begin
    if(a <= 4'b1001) begin
        if (b == 4'b1001) begin
            b <= 4'b0010;
            a <= a + 1;
        end
        else begin
            b <= b + 1;
        end
            y <= a * b;
    end
  end
end // End of Block COUNTER
endmodule // End of Module counter

[mult_tb.v]
`include "mult.v"
module mult_tb();
// Declare inputs as regs and outputs as wires
reg clock, reset, enable;
wire [3:0] a;
wire [3:0] b;
wire [6:0] y;

// Initialize all variables
initial begin
  $display ("timet clk reset enable a");
  $monitor ("%gt %b   %b     %b      %b",
          $time, clock, reset, enable, a);
  clock = 1;       // initial value of clock
  reset = 0;       // initial value of reset
  enable = 0;      // initial value of enable
  #5 reset = 0;    // Assert the reset
  #10 reset = 1;   // De-assert the reset
  #10 enable = 1;  // Assert enable
  #900 enable = 0; // De-assert enable
  #5 $finish;      // Terminate simulation
end

 

// Clock generator
always begin
  #5 clock = ~clock; // Toggle clock every 5 ticks
end

 

// Connect DUT to test bench
mult U_mult (
clock,
reset,
enable,
a, b, y
);
endmodule