[seg.v]
//-----------------------------------------------------
// This is my second Verilog Design
// Design Name : seg
// File Name : seg.v
// Function : This is a 8 bit ring-counter with
// Synchronous active high reset and
// with active high enable signal
//-----------------------------------------------------
module seg (
clock , // Clock input of the design
reset , // active high, synchronous Reset input
enable , // Active high enable signal for counter
seg_out, // 4 bit vector output of the counter
); // End of port list
//-------------Input Ports-----------------------------
input clock ;
input reset ;
input enable ;
//-------------Output Ports----------------------------
output [7:0] seg_out ;
//-------------Input ports Data Type-------------------
// By rule all the input ports should be wires
wire clock ;
wire reset ;
wire enable ;
//-------------Output Ports Data Type------------------
// Output port can be a storage element (reg) or a wire
reg [3:0] counter ;
reg [7:0] seg_out ;
reg seg_ctl ;
reg [7:0] selected ;
reg [7:0] defined;
//------------Code Starts Here-------------------------
// Since this counter is a positive edge trigged one,
// We trigger the below block with respect to positive
// edge of the clock.
always @ (posedge clock)
begin : seg // Block Name
  // At every rising edge of clock we check if reset is active
  // If active, we load the seg output with 8'b0000_0001
  if (reset == 1'b0) begin
    counter <= #1 4'b0000;
    seg_ctl <= 1'b0;
    seg_out <= 8'b0000_0000;
  end
  // If enable is active, then we increment the counter
  else if (enable == 1'b1) begin
    if (counter < 4'b1001) begin
    counter <= counter + 1;
    defined <= 4'b1001 - counter;
    end else begin
    counter <= 4'b0000;
    seg_ctl <= seg_ctl + 1;
    defined <= 8'b0000_0000;
    end
  end
end

always @ (posedge clock)
begin
  // If enable is active, then we increment the counter
  if (enable == 1'b1) begin
    if ( seg_ctl == 0 ) begin
    selected <= counter;
    end else if (seg_ctl == 1) begin
    selected <= defined;
    end
  end
end // End of Block seg_ctl

always @ (posedge clock)
begin
  // If enable is active, then we increment the counter
  if (enable == 1'b1) begin
     case (selected)
        0 : seg_out <= 8'b11111100;
        1 : seg_out <= 8'b01100000;
        2 : seg_out <= 8'b11011010;
        3 : seg_out <= 8'b11110010;
        4 : seg_out <= 8'b01100110;
        5 : seg_out <= 8'b10110110;
        6 : seg_out <= 8'b10111110;
        7 : seg_out <= 8'b11100000;
        8 : seg_out <= 8'b11111110;
        9 : seg_out <= 8'b11100110;
        default : seg_out <= 8'b11111111;
     endcase
  end
end // End of Block seg_out

endmodule // End of Module seg

[seg_tb.v]
`include "ring.v"
module ring_tb();
// Declare inputs as regs and outputs as wires
reg clock, reset, enable;
wire [7:0] counter_out;
// Initialize all variables
initial begin
  $display ("timet clk reset enable counter");
  $monitor ("%gt %b   %b     %b      %b",
          $time, clock, reset, enable, counter_out);
  clock = 1;       // initial value of clock
  reset = 0;       // initial value of reset
  enable = 0;      // initial value of enable
  #5 reset = 0;    // Assert the reset
  #10 reset = 1;   // De-assert the reset
  #10 enable = 1;  // Assert enable
  #200 enable = 0; // De-assert enable
  #5 $finish;      // Terminate simulation
end
// Clock generator
always begin
  #5 clock = ~clock; // Toggle clock every 5 ticks
end
// Connect DUT to test bench
ring U_counter (
clock,
reset,
enable,
counter_out
);
endmodule